WINGARD AI
Toward the next intelligence

Fuse, Evolve, Transcend

Wingard AI fuses chip design, EDA, and self-evolving AI agents into a single system — an engine built to carry intelligence beyond the horizon, toward next-generation superintelligence.

Begin descent
01 · Product

Spec to GDS, pursue engineering closure

Starting with MXU systolic arrays, we validate automated generation from spec to GDS, evaluation feedback, and rapid iteration across different parameter configurations. The core question is whether the system can keep reducing engineering time while maintaining controlled evolution in pass rate, coverage, and synthesis quality results.

⟡ Powered by domestic foundation models
MXU Systolic Array
128×128 Max config
~50M gates Gate count

MXU systolic array trials

128×128 ~50M gates
64×64 Scaled mid-tier
32×32 Fast regression config
16×16 ~1.84M gates

What we measure — engineering first, not benchmarks

timecore metric
Wall-clock cost of the full flow. Shipping speed is the metric that matters.
Δpass
Change in test pass rate across iterations.
Δcov.
Change in verification coverage.
ΔQoR
Quality-of-results shift, measured through synthesis.

The flow iterates rapidly and evolves itself — every run makes the next one better.

The bottleneck has shifted: no longer model capability, but the efficiency of evaluation feedback.

Chip top-level layout

Spec-to-GDS output — a complete chip top-level layout generated through the automated flow. Fmax = 705 MHz · Power = 0.811 W · Die Area = 461,371 µm² (0.68 × 0.68 mm). PPA data obtained using the OpenROAD ASAP7 7nm advanced-node test platform.

02 · Platform

Heterogeneous verification at escape velocity

One verification platform spanning GPU, FPGA, and NPU. Where others simulate, we accelerate — three orders of magnitude past open-source baselines.

Open-source baseline
Commercial tool A
~90×
Wingard heterogeneous platform
~1500×

Trail length on log scale · GPU + FPGA + NPU, unified

03 · Roadmap

One system, deeply fused

Chip development, EDA tooling, and AI agents — not three disciplines stitched together, but one vertically integrated system, compressed until it becomes something new.

CHIP DEVELOPMENT EDA AI AGENTS

Deep vertical integration

Silicon design, EDA tools, and agent design compressed into a single, coherent system — each layer feeding the others.

Self-evolving agent systems

Agents that improve their own workflows: learning from every run of every flow they execute.

New environments & infrastructure

Building the Env & Infra layer — the launchpad that the next generation of intelligence will lift off from.

AGIASI

Recursive self-improvement — systems that optimize themselves, iteration after iteration, until the curve bends upward.

Committed to building a complete AI-autonomous chip development flow, achieving a closed loop of software-hardware co-design and co-evolution.

04 · Team

Three crafts, one crew

Built by people who have shipped silicon, written the tools, and trained the agents.

CREW / CHIP

DesignHouse experts

Veterans of full chip design cycles — from architecture to tape-out.

CREW / TOOLS

EDA experts

The people who build the tools that build the chips.

CREW / AGENT

AI agent experts

Researchers and engineers crafting agents that learn, plan, and evolve.